Seminar: Secure and Fault-tolerant Computing


As fabrication technology scales, chips are becoming less reliable, thereby increasing the power and performance costs for fault-tolerance. To make matters worse, power-density is becoming a significant limiting factor for performance and System-on-Chip (SoC) design in general. In the face of such changes in the technological landscape, current solutions for fault-tolerance are expected to introduce an excessive overhead in future systems. On the other hand, attempting to design and manufacture a totally defect-/faultfree system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the performance and power consumption of a system. In the first part of the talk a new design paradigm will be presented and all the interesting points and obstacles we faced during the design process. Here, fault-tolerant systems built out of unreliable components, rather than aiming at totally fault-free chips. In addition, systems will be on-demand adaptive to various types and densities of faults, as well as to other system constraints and application requirements. For leveraging on-demand adaptation/customization and reliability at reduced cost, a new dynamically reconfigurable substrate will be designed and be combined with runtime system software support. The above will result in a well-defined, generic, and repeatable design framework for a large variety of SoCs. The proposed framework will be applied to two medical SoCs with high reliability constraints and diverse performance and power requirements.

Security and fault-tolerance are important and often interrelated aspects of computing, as induced faults may lead to leakage of secret information. Nano-CMOS and Post-CMOS novel nanoscale devices such as memristors have opened up new horizons in computing because of the promise of unprecedented integration density and performance. However, they also suffer from severe shortcomings, including unacceptable error rates due to high device defect rate, and difficulty of designing fundamental logic, memory and arithmetic circuits with these devices. In the second part of the talk novel a secure computing platforms, leveraging memristors will be presented.

Date and Time : 05-04-2017 15:00

Venue : Seminar Hall, 219 @ CET

Speaker : Jimson Mathew, IIT Patna

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